Browsing by Subject "Programming model"

Now showing items 1-3 of 3

    • Conference Object  

      The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices 

      Solinas, M.; Badia, R. M.; Bodin, F.; Cohen, A.; Evripidou, Paraskevas; Faraboschi, P.; Fechner, B.; Gao, G. R.; Garbade, A.; Girbal, S.; Goodman, D.; Khan, B.; Koliai, S.; Li, F.; Luján, M.; Morin, L.; Mendelson, A.; Navarro, N.; Pop, A.; Trancoso, Pedro; Ungerer, T.; Valero, M.; Weis, S.; Watson, I.; Zuckermann, S.; Giorgi, Roberto (2013)
      Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably ...
    • Article  

      TERAFLUX: Harnessing dataflow in next generation teradevices 

      Giorgi, Roberto; Badia, R. M.; Bodin, F.; Cohen, A.; Evripidou, Paraskevas; Faraboschi, P.; Fechner, B.; Gao, G. R.; Garbade, A.; Gayatri, R.; Girbal, S.; Goodman, D.; Khan, B.; Koliaï, S.; Landwehr, J.; Lê, N. M.; Li, F.; Lujàn, M.; Mendelson, A.; Morin, L.; Navarro, N.; Patejko, T.; Pop, A.; Trancoso, Pedro; Ungerer, T.; Watson, I.; Weis, S.; Zuckerman, S.; Valero, M. (2014)
      The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been ...
    • Conference Object  

      TFluxSCC: Exploiting performance on future many-core systems through Data-Flow 

      Diavastos, Andreas; Stylianou, Georgios; Trancoso, Pedro (Institute of Electrical and Electronics Engineers Inc., 2015)
      The current trend in processor design is to increase the number of cores as to achieve a desired performance. While having a large number of cores on a chip seems to be feasible in terms of the hardware, the development ...